Field of the Disclosure
The present disclosure relates to a display device, and more particularly, to an array substrate and a display device including the same. Although the present disclosure is suitable for a wide scope of applications, it is particularly suitable for compensating for a parasitic capacitance between a gate line and a data line and a resistance of the data line, so that the quality of an image of a display device having curve-shape corners can be improved.
Description of the Background
With the advancement of various portable electronic devices such as mobile phones and notebook computers, demand for Flat Panel Display (FPD) devices applicable to the portable electronic devices is increasing.
An liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting diode display (OLED) are actively researched as flat panel display (FPD) devices.
A display device such as an LCD device and an OLED device includes an array substrate including a thin film transistor (TFT) as an essential component. Specifically, the LCD device includes an array substrate, a color filter substrate facing the array substrate, and a liquid crystal layer formed between the two substrates. The OLED device includes an array substrate and an emission layer formed on the array substrate.
The array substrate includes a plurality of lines and a plurality of links for connecting the plurality of lines to a driving circuit. A related art array substrate will be described below with reference to the accompanying drawing.
FIG. 1 is a schematic plan view of the related art array substrate.
On an array substrate 1, a plurality of pixels 2 is defined by a plurality of gate lines GL and a plurality of data lines DL intersecting with each other. A pixel electrode 3 and a common electrode 4 are disposed on each of the plurality of pixels 2. The array substrate 1 includes a power supply unit (not illustrated) that converts a voltage input from the outside and outputs a plurality of supply voltages and a common voltage line 5 that supplies a common voltage Vcom of the power supply unit to the common electrode 4. Further, the array substrate 1 includes an active area AA where an image is displayed and a non-active area NA where a gate driving circuit unit 11 and a data pad 13 are disposed as a non-active area.
A data driving circuit unit (not illustrated) may be disposed on a Printed circuit Board (PCB) or a Chip on Film (COF) and connected to the data pad 13 through a Flexible Printed Circuit (FPC). The data pad 13 may be connected to the data lines DL through data link lines 14. The data driving circuit unit supplies a data voltage to the data lines DL through the data pad 13 and the data link lines 14.
The gate driving circuit unit (i.e., gate-in-panel) 11 sequentially supplies a scan signal (gate driving signal) for turning on a thin film transistor (TFT) formed on each pixel to each of the plurality of gate lines. Thus, the pixels on the array substrate 1 are sequentially driven. To this end, the gate driving circuit unit 11 includes a plurality of circuit blocks 12 each including a shift register and a level shifter configured to convert an output signal of the shift register into a swing width suitable for driving the TFT. Herein, a gate-in-panel (GIP)-type display device in which a thin film transistor (TFT) using amorphous silicon (a-Si) is disposed on a lower substrate (or array substrate) of the array substrate 1 and the gate driving circuit unit 11 is integrated into a display panel, i.e., the gate driving circuit unit 11 is embedded in the display panel, is employed. In this case, the gate driving circuit unit 11 may be disposed in a GIP manner on the left and right sides of the non-active area NA of the array substrate.
Unlike a display device including a rectangular screen as illustrated in FIG. 1, a display device including a screen with curved corner portions for design differentiation is being researched. In a display device, particularly a GIP-type display device, including a screen with curved corner portions unlike a display device including a rectangular screen, circuit blocks of a gate driving circuit unit are disposed corresponding to a curved shape at each corner portion of an array substrate. Accordingly, there is a change in the number of pixels which are respectively disposed on a plurality of gate lines of the display device including a screen with curved corner portions and can cause parasitic capacitances. Further, in the display device including a screen with curved corner portions unlike the display device including a rectangular screen, data lines disposed at each corner portion of the array substrate have different lengths.
Therefore, a parasitic capacitance generated at each gate line GL or each data line DL and a line resistance generated at each data line DL are different in each line. That is, a degree of delay of a signal transferred to each pixel 2 through the gate line GL is different in each gate line GL, so that a defect occurs in a displayed image. Further, a degree of delay of a data signal transferred to each pixel 2 through the data line DL is different for in data line DL, so that a defect occurs in a displayed image.